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Arithmetic

Arithmetic instructions perform integer math on register and immediate operands.

NEG

Negates a register. Has the same effect as multiplying by -1.

InstructionOperand 1Operation
NEGRegOP1 = -OP1
block->neg(REG_SP);

ADD

Adds a register or immediate value to a register.

InstructionOperand 1Operand 2Operation
ADDRegReg/ImmOP1 = OP1 + OP2
block->add(REG_SP, 1);

SUB

Subtracts a register or immediate value from a register.

InstructionOperand 1Operand 2Operation
SUBRegReg/ImmOP1 = OP1 - OP2
block->sub(REG_SP, 1);

MUL

Multiplies a register with another register or immediate value (unsigned, low half).

InstructionOperand 1Operand 2Operation
MULRegReg/ImmOP1 = OP1 * OP2
block->mul(REG_SP, 2);

MULHI

Multiplies a register with another register or immediate value and saves the higher bits.

InstructionOperand 1Operand 2Operation
MULHIRegReg/ImmOP1 = [OP1 * OP2] >> N
block->mulhi(REG_SP, 2);

IMUL

Signed multiplication of a register with another register or immediate value (low half).

InstructionOperand 1Operand 2Operation
IMULRegReg/ImmOP1 = OP1 * OP2 (signed)
block->imul(REG_SP, 2);

IMULHI

Signed multiplication saving the higher bits of the result.

InstructionOperand 1Operand 2Operation
IMULHIRegReg/ImmOP1 = [OP1 * OP2] >> N (signed)
block->imulhi(REG_SP, 2);

DIV

Performs an unsigned division. The dividend spans two registers for high and low bits.

InstructionOperand 1Operand 2Operand 3Operation
DIVRegReg/ImmReg/ImmOP1 = [OP2:OP1] / OP3
block->div(REG_SP, 0, REG_SP); // sets REG_SP to 1

IDIV

Performs a signed division. The dividend spans two registers for high and low bits.

InstructionOperand 1Operand 2Operand 3Operation
IDIVRegReg/ImmReg/ImmOP1 = [OP2:OP1] / OP3 (signed)
block->idiv(REG_SP, 0, REG_SP);

REM

Performs an unsigned modulo operation. The source spans two registers.

InstructionOperand 1Operand 2Operand 3Operation
REMRegReg/ImmReg/ImmOP1 = [OP2:OP1] % OP3
block->rem(REG_SP, 0, REG_SP); // sets REG_SP to 0

IREM

Performs a signed modulo operation. The source spans two registers.

InstructionOperand 1Operand 2Operand 3Operation
IREMRegReg/ImmReg/ImmOP1 = [OP2:OP1] % OP3 (signed)
block->irem(REG_SP, 0, REG_SP);