VTILVTIL

Conditionals

Conditional instructions evaluate a comparison between two operands and store a boolean result (0 or 1) into a destination register. They are typically used as inputs to JS.

Comparison instructions

MnemonicOp1Op2Op3Operation
TGRegReg/ImmReg/ImmOP1 = OP2 > OP3 (signed)
TGERegReg/ImmReg/ImmOP1 = OP2 >= OP3 (signed)
TERegReg/ImmReg/ImmOP1 = OP2 == OP3
TNERegReg/ImmReg/ImmOP1 = OP2 != OP3
TLRegReg/ImmReg/ImmOP1 = OP2 < OP3 (signed)
TLERegReg/ImmReg/ImmOP1 = OP2 <= OP3 (signed)
TUGRegReg/ImmReg/ImmOP1 = OP2 > OP3 (unsigned)
TUGERegReg/ImmReg/ImmOP1 = OP2 >= OP3 (unsigned)
TULRegReg/ImmReg/ImmOP1 = OP2 < OP3 (unsigned)
TULERegReg/ImmReg/ImmOP1 = OP2 <= OP3 (unsigned)

IFS - If-Select

Evaluates the second operand as a condition. If true, assigns the third operand to the destination; otherwise assigns zero.

InstructionOperand 1Operand 2Operand 3Operation
IFSRegReg/ImmReg/ImmOP1 = OP2 ? OP3 : 0
// result = (rax == rbx) ? 0xFF : 0
auto cond = block->tmp(1);
block->te(cond, X86_REG_RAX, X86_REG_RBX);
block->ifs(X86_REG_RCX, cond, 0xFF);