General Information

VTIL instructions are extremely nonrestrictive when it comes to their usage. Mixing operand sizes are usually allowed, zero extension is implicit in MOV, unlike an SSA architecture different values can be assigned to a single variable, you can mix physical registers with temporaries or virtual registers however you wish, and so on.

However in terms of instruction set definition, there are a few restrictions every instruction follows to make optimization logic simpler.

Operand types

Memory access in VTIL is not a first-class operand type - vtil::operand is a std::variant<immediate_t, register_t>. Memory reads and writes use the dedicated LDD and STR instructions, which take a base register and an immediate offset as separate operands.